1. Field of the Invention
The present invention relates to a drive circuit of a display device, and a method of testing the same, and particularly to a drive circuit of a display device having a test circuit.
2. Description of Related Art
As shown in FIG. 4, a general liquid crystal display device, which is used as a dot matrix display device, is made of a liquid crystal display panel 101, a data side drive circuit 102, a scanning side drive circuit 103, a power supply circuit 104 and a control circuit 105.
The liquid crystal display panel 101 includes: data lines 106, which are arranged on the drawing in a horizontal direction, and which extend in a vertical direction; and scanning lines 107, which are arranged on the drawing in a vertical direction, and which extend in a horizontal direction. Each pixel is made of a TFT 108, a pixel capacitor 109, and a liquid crystal element 110. A gate terminal of the TFT 108 is connected to a scanning line 107, and a source (drain) terminal thereof is connected to a data line 106. Further, to the drain (source) terminal of the TFT 108, both the pixel capacitor 109 and the liquid crystal element 110 are connected. A terminal 111 on the side where the pixel capacitor 109 and the liquid crystal element 110 are not connected to the TFT 108 is connected, for example, to a common electrode, which is not shown.
The data side drive circuit 102 outputs an analog signal voltage on the basis of a digital image signal (hereinafter referred to as data), and drives the data lines 106. The scanning side drive circuit 103 outputs a selection/non-selection voltage of the TFT 108, and drives the scanning lines 107. The control circuit 105 controls timings of drive of each of the scanning side drive circuit 103 and the data side drive circuit 102. The power supply circuit 104 generates a signal voltage, which is outputted by the data side drive circuit 102, and a selection/non-selection voltage, which is outputted by the scanning side drive circuit 103, and supplies those voltages to the respective drive circuits. As described below, the present invention relates to the data side drive circuit 102.
In many cases, the data side drive circuit 102 is made of a plurality of driver circuits each formed of a semiconductor integrated circuit device. For example, when the resolution of a liquid crystal panel is XGA (1024×768 pixels: each pixel is composed of three dots of R(red), G(green) and B(blue)), the data side drive circuit 102 is made of 8 driver circuits so that each driver circuit is designed to take partial charge of the display of 128 pixels.
FIG. 5 is a block diagram showing a general driver circuit 1, and FIG. 6 is a timing chart for each signal inputted to the driver circuit 1 shown in FIG. 5. In order to take partial charge of the display of m pixels, each driver circuit 1 outputs signals of S1 to Sn to the data lines 106 of the number n=m×3 dots. Incidentally, in order to simplify the description, the description will be provided assuming that data are serially inputted to the driver circuit 1 with a bit width of data corresponding to one output of S1 to Sn, that is, one dot of one pixel. The driver circuit 1 includes a shift register 2, a data register 3, a data latch circuit 4, a level shifter 5, a D/A converter 6 and an output circuit 7. An output of the shift register 2 of the driver circuit 1 is outputted to a subsequent driver circuit in cascade, and the data side drive circuit 102 is configured in such a way that the multiple driver circuits 1 are connected to one another in cascade.
The shift register 2 is formed of n-steps of registers and is supplied with shift start pulses and clocks. The shift register 2 sequentially shifts the start pulses at timings of the clocks, and thereby generates shift pulses (SP1) to (SPn) shown in FIG. 6.
The data register 3 is formed of n-steps of registers. The n-steps of registers are supplied in parallel with data, and sequentially hold the data, for example, at the timings of falling edges of the shift pulses (SP1) to (SPn) supplied by the shift register 2.
Once data input to every register of the data register 3 is terminated, the data latch circuit 4 is supplied with a data latch signal, and latches all the data which have been held in every register of the data register 3. As for data latched by the data latch circuit 4, a level is shifted by the level shifter 5 as needed.
The D/A converter 6 is one decoding the data of the shifted level and outputting a gradation voltage, and includes a gradation voltage generation circuit and a gradation voltage selection circuit to be described later. The gradation voltage generation circuit is supplied with a gradation reference voltage, and the gradation voltage selection circuit selects and outputs a voltage of 64 gradations, for example. The output circuit 7 amplifies an output of the D/A converter 6 and outputs the resultant output as output signals S1 to Sn. The output circuit 7 is supplied with a data latch signal and a polarity inversion signal, which are also supplied to the data latch circuit 4, and selects and outputs an output of a polarity depending on the polarity inversion signal at a timing of the data latch signal.
Next, the D/A converter 6 and the output circuit 7 are described with reference to FIG. 7. For example, in the case of a dot inversion drive system and a 262144-color display (each of R, G and B has 64 gradations), the driver circuit 1 is configured so that signal voltages of positive and negative polarities can be outputted alternately in 64 gradations from each output S1 to Sn to a common electrode. However, for the purpose of simplifying the description, FIG. 7 only shows one output in which a signal voltage of positive polarity can be outputted in 4 gradations.
A D/A converter 6 includes a gradation voltage generation circuit 11 and a gradation voltage selection circuit 12. The gradation voltage generation circuit 11 is formed of a ladder resistance (not shown) and is supplied with a gradation reference voltage so that the gradation voltage generation circuit 11 generates voltages γ1 to γ4 of 4 gradations. The gradation voltage selection circuit 12 is formed of a plurality of switches (transistors), and selects, from among the gradation voltages γ1 to γ4, a desired gradation voltage depending on data, and outputs a voltage thus selected.
The output circuit 7 includes: an AMP 7a, which amplifies and outputs an output depending on a polarity from the D/A converter 6; and a switch (hereinafter referred to as an off switch) 7b, which controls ON/OFF of an output of the AMP 7a. As shown in FIG. 6, the off switch 7b turns off an output depending on a polarity of an amplifier as an output high impedance period in a period from a rising edge of a data latch signal to a falling edge thereof. This is a transition period of the D/A converter 6, and this off switch (TOFFSW) 7b is kept off until an electric potential is determined, thus enabling high impedance (Hi-Z).
When abnormality detection of the D/A converter 6 and the output circuit 7 of the driver circuit 1 is tested, a test signal is supplied in general to cause the D/A converter 6 to select a gradation, and an output of the output circuit 7 at that time is measured. The driver circuit 1 includes a large number of switches constituting the gradation voltage selection circuit 12 in the D/A converter 6 to respond to the outputs S1 to Sn, and a test of the driver circuit for testing whether these switches operate normally becomes very complicated. In addition, a characteristic is measured, using an output of the output circuit 7, in a state where the D/A converter 6 and the output circuit 7 are connected. For this reason, when it is determined in an operation test that the characteristic is poor, it is not possible to determine which of the D/A converter 6, the output circuit 7, the gradation voltage generation circuit 11 of the D/A converter 6, or the gradation voltage selection circuit 12 has a defect causing the characteristic to become poor. As a result, a lot of time is required to investigate a cause of the defect and to take measures against the defect. To cope with such a defect, for example, a driver circuit, with which an operation test can be easily and reliably conducted in a very short period of time, is described in Japanese Patent Application Laid-open Publication No. 2002-32053.
In the Publication, a configuration is shown in which a change-over switch is provided between a ladder resistance unit and a selector unit, and in which the selector unit includes: a state change-over circuit outputting a test voltage to the selector unit; and a test control unit. Thus, a test can be conducted by disconnecting the ladder resistance unit, supplying a test voltage directly to the selector unit, and measuring an output from an amplifier unit. As a result, a quick test can be conducted without waiting the stability of an analog gradation voltage, and in addition, a test, in which a large potential difference is set between neighboring voltage lines, is made possible.
In an operation test of the driver circuit described in Patent publication, the ladder resistance unit is disconnected, however, a characteristic is measured, using an output voltage of the amplifier unit, in a state where the selector unit and the amplifier unit are connected. For this reason, when it is determined in an operation test that the characteristic is poor, it is not possible to determine which of the selector unit or the amplifier unit has a defect causing the characteristic to become poor. As a result, as in the case of the driver circuit 1, a lot of time is required to investigate a cause of the defect and to take measures against the defect.